AN2281 datasheet(12/38 Pages) STMICROELECTRONICS

12 / 38 page

Implementation on the ST7LITE35 microcontroller

AN2281

12/38

You can observe that, in order to measure the Hall sensor semi-period correctly, the LTIC

and LTTB1 ISRs must be executed by the microcontroller core in the same order in which

the related interrupts events occurred. This would normally happen if no other interrupts

service routines are executing. However in our software, a third interrupt source is enabled

(PWM update event), so a potentially erroneous situation could arise due to the interrupt

priority mechanism.

Figure 9 describes two possible situations:

Figure 9.

Multiple interrupt pending situation

Due to the higher interrupt priority of LTIC with respect to LTTB1, in both cases the LTIC ISR

is executed before LTTB1 ISR.

In this case, the value stored in the LTICR is used to reconstruct the correct sequence: if the

content of the LTICR is lower than 125, it is assumed that the LTTB1 event occurred just

before a LTIC event so that the Lite Timer overflow counter must be incremented before the

semi-period computation. On the contrary, if the LTICR contains a value higher than 125, it

is assumed that the LTIC occurred just before a Lite timer overflow (LTTB1 event). In this

case, the overflow counter must not be incremented before the semi-period computation but

it will be taken into account at the next LTIC event.

Counter 1

249

LTTB1

Captured

value << 125

LTIC Int

Hall sensor

output

Counter 1

249

LTTB1

Captured

value >> 125

LTIC Int

PWM OVF ISR execution

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