5 Debug management

AN1775

12/27

Figure 9.

Ice connector implementation

Note: 1 In order for JTAG and Chip Reset to be synchronized the J4 jumper must be fitted.

2 STR71x has a Debug Request (DBGRQS) pin, on 144-pin packages only. This active high

signal can be used to force the core to enter Debug Mode, giving the Emulation system access

to internal resources (code, registers, memory, etc). This pin must be kept LOW when

emulation is not being used.

The following table describes the JTAG connector pins:

Std Name

STR71x

Description

Function

nTRST

JTRST

Test Reset

(from JTAG

equipment)

This active LOW open-collector is used to reset the JTAG port

and the associated debug circuitry. It is asserted at power-up

by each module, and can be driven by the JTAG equipment.

TDI

JTDI

Test data in

(from JTAG

equipment)

TDI goes down the stack of modules to the motherboard and

then back up the stack, labelled TDO, connecting to each

component in the scan chain.

TMS

JTMS

Test mode

select (from

JTAG

equipment)

TMS controls transitions in the tap controller state machine.

TMS connects to all JTAG components in the scan chain as

the signal flows down the module stack.

TCK

JTCK

Test clock (from

JTAG

equipment)

TCK synchronizes all JTAG transactions. TCK connects to all

JTAG components in the scan chain. Series termination

resistors are used to reduce reflections and maintain good

signal integrity. TCK flows down the stack of modules and

connects to each JTAG component. However, if there is a

device in the scan chain that synchronizes TCK to some other

clock, then all down-stream devices are connected to the

RTCK signal on that component.

GND

(3)

nTRST

10K*

3V3

GND

(5)

TDI

(7)

TMS

(9)

TCK

(11)

RTCK

(13)

TDO

(15)

nSRST

(17)

DBGRQ

(19)

STR71x

nJTRST

JTDI

JTMS

JTCK

JTDO

nRSTIN

DBGRQS

10K*

(4)

(6)

(8)

(10)

(12)

(14)

(16)

(18)

(20)

GND

3V3

(2)

(1)

VTref

3V3

GND

10K*

JTAG Connector CN9

CONN_2*10 RA_IDC

J4

J4

* these values are given only as typical example

** The Debug acknowledge to JTAG equipment (DBGACK pin) is not used.

GND

GND

10K

47K

3V3

GND

50v

10nF

22K

TR2

TR1

BC846

BC846

Note 1

See

GND