AN1775 datasheet(9/27 Pages) STMICROELECTRONICS

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AN1775

3 Reset management

9/27

Reset management

Both the Main Voltage Regulator and the Low Power Voltage Regulator contain an LVD.

They keep the device under reset when the corresponding controlled voltage value (V18 or

V18BKP falls below 1.35V±10%).

The LVDs do not monitor V33 which supplies the I/O and analog parts of the device.

Note:

During power-on, a reset must be provided externally.

At power on, the nRSTIN pin must be held low by an external reset circuit until V33.

Figure 6 gives an example of the hardware implementation of the RESET circuit for STR71x

devices.

●

The STM1001 low-power CMOS microprocessor supervisory circuit is used to assert a

reset signal whenever the V33 voltage falls below a preset threshold or a manual reset is

asserted.

Figure 6.

Hardware reset implementation

STR71x

nRSTIN

GND

* these values are given only as typical example

V33

GND

not Reset

VCC

GND

+3V3

+3V08

STM1001T

VSS

+3V3

2K2

GND

1nF

+3V3

AN1775 bảng dữ liệu(PDF) 9 Page - STMicroelectronics