μPD46185092B, μPD46185182B, μPD46185362B

R10DS0112EJ0200 Rev.2.00

Page 10 of 35

Nov 09, 2012

Truth Table

Operation

CLK

R#

W#

D or Q

WRITE cycle

L

→ H

×

L

Data in

Load address, input write data on

Input data

DA (A+0)

DA (A+1)

consecutive K and K# rising edge

Input clock

K( t )

↑

K#( t )

↑

READ cycle

L

→ H

L

×

Data out

Load address, output data on

Output data

QA (A+0)

QA (A+1)

consecutive C and C# rising edge

Output clock

C#(t+1)

↑

C(t+2)

↑

NOP (No operation)

L

→ H

H

H

D =

×, Q = High-Z

Clock stop

Stopped

×

×

Previous state

Remarks 1. H : HIGH, L : LOW,

× : don’t care, ↑ : rising edge.

2. Data inputs are registered at K and K# rising edges. Data outputs are delivered at C and C# rising edges

except if C and C# are HIGH then Data outputs are delivered at K and K# rising edges.

3. All control inputs in the truth table must meet setup/hold times around the rising edge (LOW to HIGH) of

K. All control inputs are registered during the rising edge of K.

4. This device contains circuitry that ensure the outputs to be in high impedance during power-up.

5. Refer to state diagram and timing diagrams for clarification.

6. It is recommended that K = K# = C = C# when clock is stopped. This is not essential but permits most

rapid restart by overcoming transmission line charging symmetrically.