Example V

UM1763

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DocID026335 Rev 1

Figure 8. SMED 5 state machine

The main code simply takes care of initializing the I/O pins, it also enables the PLL

generating the 96 MHz clock for the SMEDs. Then it properly sets the DAC, the CPP2 and

CPP3 analog comparators so to configure them according to the high and low threshold

values. Finally it enables the SMED 5. As everything is set and since now everything will be

controlled by the SMED 5, the STM8 processor is halted to reduce power consumption.

Let's note that actually the SMED 5 is configured in a way that feedback from comparators

makes the PWM5 toggle. If the comparator feedback is missing, it gets stuck. Possible

evolution of this exercise can be to try modifying the finite state machine, so that the PWM5

restarts toggling after a max_time the SMED 5 gets stuck in a state.