PM0222 datasheet(12/33 Pages) STMICROELECTRONICS

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GPIO / IOs management

PM0222

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DocID025476 Rev 1

GPIO / IOs management

Brain embeds 11 I/Os with a specific muxing: three different modes for each I/O (see

Table 5). The purpose of this chapter is to explain how to manage these modes. All GPIO

registers are described in a structure defined in the Brain header file (.h) provided by

STMicroelectronics. The GPIO registers are available at the following address in the

memory map:

GPIO APB base address: 0xA000_0000

5.1

I/O configuration

Before using the examples provided below, GPIO module has to be enabled on the CRMU

side (see Section 3.1: Peripheral clock gating).

5.1.1

I/O mode

To select a mode for an I/O, the GPIO_MODE register is used (see Figure 1: GPIO_MODE

configuration). Two bits are used to configure the I/O. After a reset, serial mode 0 (see

Table 5: GPIO modes) is the default configuration.

Table 5. GPIO modes

Ref.

Serial mode 0

Serial mode 1

GPIO port mode

GPIO_MODE_W = “00”

GPIO_MODE_W = “01”

GPIO_MODE_W = “10”

Signal

Type

Signal

Type

Signal

Type

IO0

SW_TDIO/J

TAG TMS

I/O

UART_CTS

GPIO0

I/O

IO1

SW_TCK/JT

AG TCK

UART_RTS

GPIO1

I/O

IO2

I2C2_SCL

UART_TXD

GPIO2

I/O

IO3(1)

1. In serial mode 0, IO3 must be configured as an I2C mode pad (i.e. I2C_CONF[1] = 1).

In serial mode 1 and GPIO port mode, IO3 must be configured as normal mode (I2C_CONF[1] = 0).

I2C2_SDA

I/O

UART_RXD

GPIO3

I/O

IO4

JTAG TDO

GPIO4

I/O

IO5

JTAG TDI

GPIO5

I/O

IO6(2)

2. After reset, IO6 outputs the 80 MHz clock divided by five.

Divided

CLK80M

CLK32K

GPIO6

I/O

IO7

I2C1 SCL

I/O

SPI_CLK

I/O

GPIO7

I/O

IO8

I2C1 SDA

I/O

SPI_OUT

GPIO8

I/O

IO9

SPI_CS

GPIO9

I/O

IO10

SPI_IN

GPIO10

I/O

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