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AN4022 bảng dữ liệu(PDF) 11 Page - STMicroelectronics |
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AN4022 bảng dữ liệu(HTML) 11 Page - STMicroelectronics |
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11 / 15 page ![]() DocID022589 Rev 2 11/15 AN4022 Predicted results versus measured results 15 Figure 16. Gap between measured and calculated values versus current rate of rise Figure 17. Parasitic inductance There are three considerations regarding the first spike: This calculation of the VCL for this first spike is not correct for a bidirectional device or a rail to rail plus Transil™ device (USBULC6-2F3 for example), because in this case, a parameter called VFP linked to one of the junctions in forward conduction induces another added spike voltage. This VFP depends on the diode technology and cannot be easily evaluated. We see here the importance of the parasitic inductances especially the ground inductance return pass. The lower the value of this inductance, the lower the value of this transient voltage. This spike is not the most critical for the device to protect against because I/O’s IC circuits are dimensioned to withstand short pulses with these levels, similar to machine model ESD tests, for example. From Figure 14 and Figure 15 we see the predicted values for the clamping voltages at 30 ns and 60 ns are very close to the measured results, assuming the dynamic characteristic measured in these conditions are consistent, even at high current and voltage levels. Note: The study in forward polarity gives the same kind of results. 0 10 20 30 40 50 0 20 40 60 80 100 ΔV (V) CL dI/dt (A/ns) 0.0 0.2 0.4 0.6 0.8 1.0 0 20 406080 100 Average value: 0.5 nH dI/dt (A/ns) L (nH) PARASITIC |
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