AN3994 datasheet(39/53 Pages) STMICROELECTRONICS

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AN3994

MOSFET critical parameters in high switching environments

Doc ID 022380 Rev 1

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On the contrary, when high drain currents/high

ΔI/dt are involved, the induced voltage V

becomes large enough to significantly interfere with the gate bias.

A second order effect related to the source inductance is that RGtot, Ls, and Ciss (at turn-on)

are the RLC components of a series resonant circuit, as shown in Figure 46.

Figure 46.

Simplified equivalent series resonant model of the driving circuit of a

MOSFET

As far as the resonance aspect is concerned, the phenomenon is due to the Ls inductor and

the MOSFET input capacitor energy exchange (if turn-off is considered, the capacitor

involved is the drain source Cds). This results in the output current (gate current IG) and

voltage oscillatory spikes which can lead to unwanted turn-on if the VGS voltage reaches the

threshold value.

The Q factor of the resonant circuit which is also related to the Ls value and is responsible of

the output signal time response, can be reduced by increasing the total gate resistor

components along the driving loop (which comprises the external RG, the MOSFET intrinsic

RG and the driver output impedance).

If especially small sizes are involved, a higher gate resistor causes under damped

oscillations in the gate drive voltage waveforms but results in turn-on/turn-off time widening.

On the other hand, if RG values need to be lowered to optimize the energy losses at turn-on

and turn-off, the user must accept the possibility of spurious gate driving waveforms.

7.3

Minimizing common source inductance: layout optimization

and Kelvin source connection on STW77N65M5

The negative impact on turn-on and turn-off energy losses, due to the source inductance,

can be minimized by taking particular care of the layout during the design phase: the gate

driving loop should be as short as possible to minimize the total parasitic loop inductance

and more precisely, the common source wiring between the commutation loop and the gate

loop should be as short as possible (ideally zero) to minimize the slowing action of the Ls on

the drain current. This could be accomplished by placing the driving stage GND directly

connected to the source pin of the switch or very close to it, as shown in Figure 47.

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