AN4504 datasheet(18/41 Pages) STMICROELECTRONICS

18 / 41 page

Interrupt generation

AN4504

18/41

DocID026419 Rev 1

Interrupt generation

The L3G4200D interrupt signal can be configured in a very flexible way, allowing to

recognize independent rotations of the X-,Y- and Z-axis. The interrupt signal can be driven

to the INT1 pin. The INT2 pin is dedicated to DRDY and FIFO interrupts.

5.1

Interrupt pin configuration

The device is provided with two pins which can be activated to generate either the data-

ready or the interrupt signals. The functionality of the pins is selected through

CTRL_REG3(22h). Refer to Table 15 and to the block diagram given in Figure 6.

Figure 6. Interrupt signals and interrupt pins

Table 15. CTRL_REG3 register

I1_Int1

I1_Boot

H_Lactive

PP_OD

I2_DRDY

I2_WTM

I2_ORun

I2_Empty

Table 16. CTRL_REG3 description

I1_Int1

Interrupt enable on the INT1 pin. Default value 0. (0: Disable; 1: Enable)

I1_Boot

Boot status available on INT1. Default value 0. (0: Disable; 1: Enable)

H_Lactive

Interrupt active configuration on INT1. Default value 0. (0: High; 1:Low)

PP_OD

Push-pull / Open drain. Default value: 0. (0: Push-pull; 1: Open drain)

I2_DRDY

Date Ready on DRDY/INT2. Default value 0. (0: Disable; 1: Enable)

I2_WTM

FIFO Watermark interrupt on DRDY/INT2. Default value: 0. (0: Disable; 1: Enable)

I2_ORun

FIFO Overrun interrupt on DRDY/INT2 Default value: 0. (0: Disable; 1: Enable)

I2_Empty

FIFO Empty interrupt on DRDY/INT2. Default value: 0. (0: Disable; 1: Enable)

AN4504 bảng dữ liệu(PDF) 18 Page - STMicroelectronics