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AN4350 bảng dữ liệu(PDF) 12 Page - STMicroelectronics |
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AN4350 bảng dữ liệu(HTML) 12 Page - STMicroelectronics |
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12 / 34 page ![]() Circuit description and design guidelines AN4350 12/34 DocID025181 Rev 1 Equation 19 Replacing Equation 1, Equation 13, and Equation 18 in Equation 17, the RSENSE resistor results: Equation 20 The resistors RSENSE, RFB, RDMG, ROS, RCS, RPF determine the output voltage and the maximum deliverable current setting - suggested accuracy of these parameters is 1%. 2.5 Output filter The output filter has to be designed to respect the output voltage ripple specification ( VOUTpk-pk). In this kind of application, the single-stage high power factor, the high frequency ripple at the switching frequency can be neglected respect to the low frequency ripple at double line frequency (100/120 Hz). The output capacitor value can then be estimated using Equation 21: Equation 21 For this design, three output capacitors of 330 F/64 m/35 V have been selected. 2.6 Voltage control loop compensation As mentioned in Section 2.3 the voltage control loop must have frequency bandwidth much lower than the “control current loop” to avoid any interaction between the two loops. The current loop “works” at the double of line input frequency (100 - 120 Hz), resulting in suggested voltage loop bandwidth in the range of 5 - 10 Hz (BWCV < 1/10 of current loop bandwidth). The small signal system voltage loop gain can be estimated considering the equivalent schematic in Figure 5. Equation 22 Gloop_CV(s) = Gp(s) Gc(s) = [Gpwm Gps(s)] [Gea(s) Gsh(s) Gfb] VAUX VIN NAUX NP -------------- = RSENSE 1 2 --- NAUX NS -------------- RCS RPF ----------- 1 IOUT CC ---------------------- VinRMS MIN 1 VR V inRMS MIN ------------------------------------------- + ----------------------------------------------------------- = CoutMIN 0.4 -------- IOUT MAX fline V OUT PK PK – ------------------------------------------------------- 0.4 -------- 310mA 50Hz 0.75V ------------------------------------ 1005 F == |
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