AN3286 datasheet(25/42 Pages) STMICROELECTRONICS

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AN3286

Testing the board

Doc ID 17998 Rev 1

25/42

If the load power demand exceeds the converter power capability, the FB pin voltage

exceeds VFBlin, the internal pull-up of the pin is disconnected and the pin starts sourcing

a 3 µA current that charges the capacitor C7 of the schematic in Figure 2.

As the voltage across the FB pin reaches the VFB_olp threshold (4.8 V typical), the VIPer25

stops switching (see Figure 26) and is not allowed to switch again until the VDD voltage has

fallen below VDD_RESTART (4.5 V typical) and risen again up to VDD_ON (14 V typical, see

Figure 25). Therefore the value of C7 defines the maximum duration of an overload event

without shutting down the IC.

If the overload (or short-circuit) is not removed, the protection is tripped again and the

system works in auto-restart mode (see Figure 25, 27, and 29).

If the overload disappears, the converter resumes normal working mode at the first VDD

recycling, as shown in Figure 29 and 30.

C7 is needed because usually the value of the C6 capacitor, coming from the loop stability

calculations, is too small to ensure an OLP delay time long enough to bypass the initial

output voltage transient at startup. The value of C7 can be chosen high enough to provide

the needed delay, and the value of R12 chosen so that the R12-C7 pole does not affect the

stability of the loop.

During an overload the converter is operated at a very low duty cycle, being the MOSFET

kept in the OFF state for most of the time. This results in a very low average power

throughput, which is safe for the power elements in this condition.

Figure 25.

OLP: output short and protection

tripping

Figure 26.

OLP: output short and protection

tripping - zoom

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