AN2335 datasheet(11/40 Pages) STMICROELECTRONICS

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AN2335

Digital interfaces

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Transfer when Master is receiving (reading) multiple bytes of data from slave

Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number

of bytes transferred per transfer is unlimited. Data is transferred with the Most Significant bit

(MSb) first. If a receiver can’t receive another complete byte of data until it has performed

some other function, it can hold the clock line, SCL LOW to force the transmitter into a wait

state. Data transfer only continues when the receiver is ready for another byte and releases

the data line. If a slave receiver doesn’t acknowledge the slave address (i.e. it is not able to

receive because it is performing some real time function) the data line must be left HIGH by

the slave. The Master can then abort the transfer. A LOW to HIGH transition on the SDA line

while the SCL line is HIGH is defined as a STOP condition. Each data transfer must be

terminated by the generation of a STOP (SP) condition.

In order to read multiple bytes, it is necessary to assert the most significant bit of the sub-

address field. In other words, SUB(7) must be equal to 1 while SUB(6-0) represents the

address of first register to read.

In the presented communication format MAK is Master Acknowledge and NMAK is No

Master Acknowledge.

4.1.2

I2C Subsequences

In order to better define subsequences and to clarify line SCL and SDA behavior, a

description containing discrete value of SCL and SDA will follow. In column there is the

value present on line SCL and SDA in discrete timing. These simple subsequences are

used to realize complex commands described in the following paragraph.

Master

SAD + W

SUB

SAD + R

MAK

Slave

SAK

DATA

Master

MAK

NMAK

Slave

DATA

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