AN1049 datasheet(20/24 Pages) STMICROELECTRONICS

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Table A1. Typical VE ranges

Mains

110Vac

± 20%

220/240 Vac

± 20%

Universal

Vin

100

÷ 175Vdc

215

÷ 370Vdc

100

÷ 400Vdc

PinTmax/PinTmin

VR = 50V

33.3

÷ 38.9

1.37

40.6

÷ 44.0

1.18

33.3

÷ 44.4

1.78

VR = 100V

50.0

÷ 63.6

1.62

68.3

÷ 78.7

1.33

50.0

÷ 80.0

2.56

VR = 150V

60.0

÷ 80.8

1.81

88.4

÷ 106.7

1.46

60.0

÷ 109.1

3.31

The peak primary current is no more uniquely related to Pin but now depends also on VE (i.e. Vin):

Ippk(CCM) =

Vin

⋅

TON

⋅ ∆Ip =

⋅ ZE

(A11).

It is possible to prove that Ippk is minimum when VE = VET for a given Pin (>PinTmin), that is at the transi-

tion, then it will be maximum for VE = VEmin (i.e. for Vin = Vinmin).

It is convenient to classify flyback converters on the basis of their maximum input power Pinmax:

Pinmax

Poutmax

+ Pextra

(A12),

being Poutmax their rated output power, Pextra some extra output power provided for transients or tempo-

rary overloads and

η their efficiency, as follows:

Pinmax < PinTmin (

⇒ VET < VEmin): DCM flyback;

PinTmin < Pinmax < PinTmax (

⇒ VEmin < VET < VEmax): MCM (Mixed Conduction Mode) flyback ;

Pinmax > PinTmax (

⇒ VET > VEmax): CCM flyback.

Peak Current Mode Control Basics

The following relationships describing the "peak" current mode control are based on the architecture

shown in fig. A1 and implemented by the L5991.

From the inspection of the schematic of fig. A1 it is possible to find the relationship between the peak pri-

mary current (Ippk), the peak voltage (Vcspk) on the (-) input of the PWM comparator and the output volt-

age (VCOMP) of the error amplifier (E/A):

VCOMP

= VC + 2 ⋅ Vf = 3 ⋅ Vcspk + 2 ⋅ Vf = 3 ⋅ (Rs ⋅ Ippk + Vo) + 2 ⋅ Vf

(B1)

where Vf is the forward drop on each "zero duty cycle diode" (0.7V typ.) and Vo a DC offset voltage that

may be applied on the (-) input of the PWM comparator (that is on the current sense pin of the L5991).

VC, the voltage downstream the two zero duty cycle diodes (and applied on the x3 divider), despite not

really available, can be considered for convenience.

Considering the 1V clamp on the (+) input of the current sense comparator, VC will be included between

0 and 3 V, and the useful swing of VCOMP between 2

⋅ Vf and 3 + 2 ⋅ Vf volt.

Actually, equation (B1) neglects the so-called "delay to output" of the PWM controller, that is the propa-

gation delay of the current sense path (PWM comparator + latch + driver). During this time, the switch is

still ON and the input current keeps on ramping up, despite Vcs has already hit the internal level on (-)

input of the PWM comparator.

This time lag (TDELAY, 70 ns typ. 100 ns max.) is compensated by the voltage loop when the system is

regulating: VCOMP is slightly lower than the value predicted by (B1) but the phase margin of the control

loop gain gets less. Instead, when the error amplifier is saturated high and the pulse-by-pulse limiting is

tripped, TDELAY causes the peak current Ippk to be larger than the expected limit 1 / Rs. As illustrated in

fig. B1, the effect is more pronunciated as the input voltage increases.

AN1049 APPLICATION NOTE

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