AN4129 datasheet(21/39 Pages) STMICROELECTRONICS

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AN4129

Circuit description and design guidance

Doc ID 023314 Rev 1

21/39

4.6.3

Reflected voltage

For PFC-flyback transition mode power converters on US 120 V lines the best reflected

voltage choice is 110 to 130 V. This range gives the best converter efficiency. Copper losses

can be spread between the primary and secondary windings about equally, and the FET's

turn-on losses discharging circuit capacitance are quite low.

A turns ratio of 2:1 primary : secondary was selected, placing reflected voltage at about 112

V at full undimmed output.

4.6.4

Primary inductance

Assuming the FET on-time takes up half the cycle time:

Equation 2

A value of 900 µH was selected because additional time is required for the resonant drain

voltage fall time of the transition mode converter.

4.6.5

Leakage inductance

This should be as low as possible - energy stored here does not contribute to LED power

and must be dissipated as heat. The transformer used has about 8 µH of leakage

inductance, as seen from the primary winding.

4.6.6

Auxiliary winding turns ratio

Operating voltage for the HVLED815PF depends on the LED voltage and this turns ratio.

The LED winding (secondary) voltage reflects to the flyback voltage on all windings. The

turns ratio from the secondary to the auxiliary winding determines the auxiliary voltage, both

for voltage regulation (open load protection) and for the Vcc power supply.

4.6.7

Final transformer specifications

Winding ratios, primary inductance, peak currents, and other specifications are shown in the

schematic. The vendor's specification sheet appears in Figure 42.

4.7

DMG pin (R6, R7)

This single pin performs several functions; voltage limiting, zero current detection, and

correction for line voltage changes. Its operation is discussed thoroughly in the datasheet

and is only summarized here. The internal circuit is also used in ST's HVLED805 and Altair

chips. The datasheets and application notes for these parts can give additional insight into

the pin operation.

Design begins with compensation for the internal comparator's propagation delay. At high

line voltage the slope of FET current vs. time is higher, so for the same comparator

reference voltage the current overshoots more than at low line. This is compensated by

adding an offset proportional to line voltage to the comparator's reference input. R6, in

conjunction with an internal resistor (RFF) of about 45

Ω, sets this compensation.

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