PDP Sustain circuit

AN2503

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c)

Energy Recovery phase: T4, T5, T6, and T11 are turned ON, and the current flows

from Cp to CS2.

Figure 20.

d)

Zero voltage Clamp, T4, T5, T6, T10 are turned ON.

Figure 21.

Circuit scheme – clamping to ground

It can be noted that during sustain phase, path switches T5 and T6 are always turned ON,

and they see both energy recovery current and discharge current which explains the need

for low voltage drop devices.

3.3

Reset phase

At the end of each subfield, the cells are reset applying a positive ramp voltage followed by a

negative one.

During positive reset, T10, T5, T7 are turned ON. During negative reset T10 and T8 are

turned ON.

Vs

Vs

Vs

Vset

L7

T9

T10

T8

T12

T11

-Vreset

Cp

CS1

CS2

L1

D7

D8

D6

D5

T7

D1

Vs

T3

T2

T1

T4

T6

T5

D2

D4

D3

V

V

V

Vse

L

T

T1

T

X-Electrode

Y

-

E

l

e

c

T1

T1

C

CS

CS

L

D

D

D

D

T

D

V

T

T

T

T

D

D