Read and clear status operation

TN0897

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Doc ID 023176 Rev 2

6.2

Format of data shifted out at SDO during read and clear

status operation

Figure 12.

SDO Frame composition during READ and CLEAR operation

Failures are indicated by activating the corresponding bit of the <Global Status> register.

The returned data byte(s) represent(s) the content of the register to be read.

Figure 13.

Read and clear status operation - 16 bit frame

Global status register

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Global Error

Flag (GEF)

Comm

Error

Not (Chip Reset

OR Comm Error)

TSD / chip

overload

Device

specific

Device

specific

Fail

Safe

Data byte 1 - content of addressed status register or configuration register

MSB

LSB

D7

D6

D5

D4

D3

D2

D1

D0

1.

Only for 24-bit SPI frame width.

MSB

LSB

D7

D6

D5

D4

D3

D2

D1

D0

0

0

0

0

0

0

0

0

A0

A1

A2

A3

A4

A5

0

1

CSN

SDI

Command

D0

D1

D2

D3

D4

D5

D6

D7

Fail

Safe

Dev

spec

Dev

spec

TSD /

Chip

OVL

NOT

(Chip

Res

OR

Comm

Err)

Com

Error

GEF

SDO

Global Status

Content of addressed status register

or ‚Configuration’ Register (8 bit)

GAPGCFT00724