SPI communication flow

TN0897

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Doc ID 023176 Rev 2

<WD Trigger>: this Bit is reserved to trigger the watchdog. The precise procedure required

to serve the watchdog is device specific and defined in the product datasheet. The bit is

reserved if the device has no watchdog.

<Masking>: bits 1, 2 and 3 allow masking of the corresponding bit in the <Global Status>

register. If a Status Bit is masked, it is excluded from the <Global Error Flag> composition,

i. e. the information is still indicated in the <Global Status> register but it is not contributing

to the <Global Error Flag> (Bit 7 of the <Global Status> register).

1 = corresponding bit is masked, 0 = corresponding bit is not masked

Table 5.

Configuration register

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Device

specific

fault mask

Device

specific

fault mask

Device

specific

fault mask

Device

specific

fault mask

Masking

Bit 3 of

<Global

Status>

register

Masking

Bit 2 of

<Global

Status>

register

Masking

Bit 1 of

<Global

Status>

register

WD

Trigger