AN4092 datasheet(31/38 Pages) STMICROELECTRONICS

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AN4092

Reset

Doc ID 023080 Rev 2

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Reset

In the SPC564Axx / SPC563Mxx devices two reset related pins are implemented:

●

/RESET

●

/RSTOUT

being respectively the reset input and the reset output.

5.1

/RESET

The /RESET pin is an active low input. The RESET pin is asserted by an external device

during a power-on or external reset. The internal reset signal asserts only if the RESET pin

asserts for 10 clock cycles.

Assertion of the /RESET pin while the device is in reset causes the reset cycle to start over.

The /RESET pin has a glitch detector which detects spikes greater than two clocks in

duration that fall below the switch point of the input buffer logic of the VDDEH input pins.

The switch point lies between the maximum VIL and minimum VIH specifications for the

VDDEH input pins.

5.2

/RSTOUT

The /RSTOUT pin is an active low output that uses a push/pull configuration. The /RSTOUT

pin is driven to the low state by the MCU for all internal and external reset sources.

Depending on the PLL configuration, External Reference or Crystal Mode, the /RSTOUT pin

is asserted after a different delay depending on the reset source(o), plus four cycles for

sampling of the configuration pins.

The /RSTOUT pin can also be asserted by a write to the SER bit of the System Reset

Control Register (SIU_SRCR).

5.3

Reset source description

The table below summarizes the reset sources and their effect on the system.

Refer to the device reference manual.

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