AN4092 datasheet(19/38 Pages) STMICROELECTRONICS

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AN4092

FMPLL and crystal oscillator

Doc ID 023080 Rev 2

19/38

FMPLL and crystal oscillator

The frequency modulated phase locked loop (FMPLL) allows the user to generate high

speed system clocks from a crystal oscillator or from an external clock generator. The

onchip oscillator is designed to operate in the range 4-40MHz (SPC563Mxx: 4-20MHz). The

frequency modulation is register programmable (frequency and depth). The clock quality

module (CQM) provides loss-of-clock detection for the FMPLL reference and output clocks

comparing these with the internal RC reference(k). The lock detection circuitry reports when

the FMPLL has achieved frequency lock and continuously monitors lock status to report

loss-of-lock conditions.

The FMPLL is powered through the VDDPLL/VSSPLL supply couple while the onchip

oscillator is powered by the internal 3.3V regulator (or external 3.3V supply).

Figure 7.

System clock diagram

2.1

Crystal oscillator and external circuitry

The crystal oscillator circuit is designed and used to provide reference clock to the PLL.

Input to the circuit is a sinusoidal input generated by a crystal with an amplifier. Output is a

square wave which is used as a reference clock to the PLL.

The type of oscillator is a Pierce CMOS crystal one. This oscillator, however, has an

Automatic Level Controller where the amount of current sourced into the amplifier is

inversely proportional to the amplitude of the input signal EXTAL. The EXTAL and XTAL

signals are then fed to inputs of a comparator to generate a square-wave signal.The crystal

oscillator may provide a reference clock to the FMPLL.

The internal RC oscillator cannot be used as system clock.

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