DocID026923 Rev 1

5/14

AN4587

What causes Iib spikes

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Figure 5 and 6 are a snapshot scope of the current in the input pins of the TSZ121 at

different Vcc while Figure 7 and 8 are simulations of the current in the input pins. Effectively,

we can see that when the Vcc is low, the amplitude of the spikes on the input bias current is

largely attenuated.

The input bias current of the TSZ121 datasheet is an average of this current over a long

period.

This average DC current can also be expressed mathematically.

We can see in Figure 1 that there are two stages of MOS, meaning that the charges are

injected twice at every clock cycle. So, we can deduce a net DC current on the inputs given

by Equation 2.

Equation 2

Where fchop is the chopping frequency.

Figure 5. TSZ121 input bias current spike,

Vcc = 5.5 V

Figure 6. TSZ121 input bias current spike,

Vcc = 1.8 V

Figure 7. Simulation of input bias current,

Vcc = 5.5 V

Figure 8. Simulation of input bias current,

Vcc = 1.8 V

2

fchop

Q

⋅⋅

=

(2)