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AN4035 bảng dữ liệu(PDF) 30 Page - STMicroelectronics

tên linh kiện AN4035
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AN4035 bảng dữ liệu(HTML) 30 Page - STMicroelectronics

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Nexus Read/Write access block
AN4035
30/41
Doc ID 022669 Rev 2
Figure 20.
Read/Write access data register (RWD)
RWA is shown in Figure 21.
Figure 21.
Read/Write access address register (RWA)
4.1
Nexus register access
Access to the Nexus registers is enabled by loading the Nexus3-Access instruction
(0b00_0111_1100) into the OCMD of the OnCE. Once the Nexus3-Access instruction has
been loaded, reading/writing a Nexus register requires two passes through the DR path the
OnCE TAP controller state machine that are detailed below.
1.
The first pass through the DR selects the Nexus register to be accessed and whether
the access is a read or a write. This is achieved by loading an 8-bit value LSB first into
the JTAG Data Register (DR). The format of this register is described in Table 7.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
Read/Write Data
W
Reset
000
0000
00000
0000
Nexus
Reg
0xA
15
14
13
12
11
10
9
87654
3210
R
Read/Write Data
W
Reset
000
0000
00000
0000
Nexus
Reg
0xA
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
Read/Write Address
W
Reset
0000
00000
0000
000
Nexus
Reg
0x9
15
14
13
12
11
10
987
6543
210
R
Read/Write Address
W
Reset
0000
00000
0000
000
Nexus
Reg
0x9



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