9-16

February 1998

HSP45240/883

Address Sequencer

Features

• This Circuit is Processed in Accordance to MIL-STD-

883 and is Fully Conformant Under the Provisions of

Paragraph 1.2.1.

• Block Oriented 24-Bit Sequencer

• Configurable as Two Independent 12-Bit Sequencers

• 24 x 24 Crosspoint Switch

• Programmable Delay on 12 Outputs 9-

• Multi-Chip Synchronization Signals

• Standard

µP Interface

• 100pF Drive on Outputs

• DC to 40MHz Clock Rate

Applications

• 1-D, 2-D Filtering

• Pan/Zoom Addressing

• FFT Processing

• Matrix Math Operations

Description

The Intersil HSP45240/883 is a high speed Address

Sequencer which provides specialized addressing for func-

tions like FFTs, 1-D and 2-D filtering, matrix operations, and

image manipulation. The sequencer supports block oriented

addressing of large data sets up to 24 bits at clock speeds

up to 40MHz.

Specialized addressing requirements are met by using the

onboard 24 x 24 crosspoint switch. This feature allows the

mapping of the 24 address bits at the output of the address

generator to the 24 address outputs of the chip. As a result,

bit reverse addressing, such as that used in FFTs, is made

possible.

A single chip solution to read/write addressing is also made

possible by configuring the HSP45240 as two 12-bit

sequencers. To compensate for system pipeline delay, a pro-

grammable delay is provided on 12 of the address outputs.

The HSP45240 is manufactured using an advanced CMOS

process, and is a low power fully static design. The configu-

ration of the device is controlled through a standard micro-

processor interface and all inputs/outputs, with the exception

of clock, are TTL compatible.

Block Diagram

Ordering Information

PART NUMBER

TEMP.

PACKAGE

PKG.

NO.

HSP45240GM-25/883

-55 to 125

68 Ld PGA

HSP45240GM-33/883

-55 to 125

68 Ld PGA

HSP45240GM-40/883

-55 to 125

68 Ld PGA

24

DLYBLK

OUT12-23

12

OUT0-11

12

STARTIN

STARTOUT

ADDVAL

DONE

BLOCKDONE

OEH

OEL

BUSY

START

CIRCUITRY

SEQUENCE

GENERATOR

SWITCH

CROSS-POINT

REG

DELAY

1-8

PROCESSOR INTERFACE

D0-6, CS, A0, WR

File Number

2816.3

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

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