9

Dissipation In Multiple Outputs

HIP0080, HIP0081The HIP0080 and HIP0081 Power

Drivers have multiple MOS Output Drivers and require

special consideration with regard to maximum current and

dissipation ratings. While each output has a maximum

current specification consistent with the device structure,

all such devices on the chip can not be simultaneously

rated to the same high level of peak current. The total

combined current and the dissipation on the chip must be

adjusted for maximum allowable ratings, given

simultaneous multiple output conditions.

HIP0080, HIP0081For the HIP0081, the maximum positive

output current rating is 2.2A when one output is ON. When

ALL outputs are ON, the rating is reduced to 1.5A because

the total maximum current is limited to 6A. For any given

application, all output drivers on a chip may or may not have a

different level of loading. The discussion here is intended to

provide relatively simple methods to determine the maximum

dissipation and current ratings as a general solution and, as a

special solution, when all switched ON outputs have the same

current loading.

General Solution

HIP0080, HIP0081A general equation for dissipation

should specify that the total power dissipation in a

package is the sum of all significant elements of

dissipation on the chip. However, in Power BiMOS Circuits

very little dissipation is needed to control the logic and

predriver circuits on the chip. The overall chip dissipation

channel where the current, I is the output current and the

output drivers is:

of each output driver without regard to uniformity of

dissipation in each MOS channel. The dissipation loss in

an NMOS channel is given in Equation 2 where the current,

I, is determined by the output load when the channel is

the circuit design, level of gate voltage and the chip

the interconnecting metal on the chip and bond wires of the

package.

HIP0080, HIP0081The temperature rise in the package

and the thermal resistance,

θ

heat flow solution is:

HIP0080, HIP0081or:

HIP0080, HIP0081Since this solution relates only to the

package, further consideration must be given to a practical

heat sink. The equation of linear heat flow assumes that

the thermal resistance from Junction-to-Ambient (

θ

the sum of the thermal resistance from Junction-to-Case

and the thermal resistance from Case (heat sink)-to-

Ambient. The Junction-to-Ambient thermal resistance,

θ

JA

is the sum of all thermal paths from the chip junction to the

expressed as:

FIGURE 4. SINGLE PULSE ENERGY TEST SHOWING THE

FAILURE BOUNDARY FOR EACH HIP0080 OUT-

PUT STRESSED TO POINT OF FAILURE

FIGURE 5. SINGLE PULSE ENERGY TEST SHOWING THE

FAILURE BOUNDARY FOR EACH HIP0081 OUT-

PUT STRESSED TO POINT OF FAILURE

0.1

1

10

100

1000

100

1000

10000

PULSE WIDTH TIME (ms)

HIP0080 SINGLE PULSE

SAFE

OPERA

TING

AREA

ENERGY vs TIME

NOTE: SAFE OPERATING AREA

BELOW DOTTED LINE

0.1

1

10

100

1000

100

1000

10000

PULSE WIDTH TIME (ms)

HIP0081 SINGLE PULSE

ENERGY vs TIME

NOTE: SAFE OPERATING AREA

BELOW DOTTED LINE

D

P

k

k1

=

n

∑

=

(EQ. 1)

P

k

I

2

r

DS ON

()

×

=

(EQ. 2)

T

J

T

C

P

D

θ

JC

×

+

=

(EQ. 3)

(EQ. 3A)

T

C

T

J

P

D

θ

JC

×

–

=

θ

JA

θ

JC

θ

CA

+

=

(EQ. 4)

HIP0080, HIP0081