CDP1852CD datasheet(6/9 Pages) INTERSIL

tên linh kiện	CDP1852CD

Giải thích chi tiết về linh kiện	Byte-Wide Input/Output Port

PDF	9 Pages

Scroll/Zoom	100%

nhà sản xuất	INTERSIL [Intersil Corporation]

Trang chủ	http://www.intersil.com/cda/home

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FIGURE 4. MODE 0 INPUT PORT TIMING WAVEFORMS AND TRUTH TABLES

FIGURE 5. INPUT PORT MODE 0 FUNCTIONAL DIAGRAM AND WAVEFORMS - TYPICAL OPERATION

tWW

tSW

tDH

tDS

tSDO

tDOH

tSSR

tCSR

tRSR

tCLR

HIGH

IMPEDANCE

DATA BUS

CLEAR

DATA IN

CLOCK

CS1 - CS2

(NOTE 1)

MODE 0 TRUTH TABLE

CLOCK

† CS1-CS2

CLEAR

DATA OUT EQUALS

High Impedance

010

011

Data Latch

Data In

† CS1

• CS2: CS1 = 1, CS2 = 1

SERVICE REQUEST TRUTH TABLE

CLOCK

CS1 or CS2

or CLEAR

SR/SR

NOTE 1. CS1

• CS2 is the overlap of CS1 = 1 and CS2 = 1.

CS2

CDP1852

DATA BUS

CS1

MODE

CLOCK

STROBE

DATA FROM

PERIPHERAL

VSS

CDP1802

MRD

MEMORY

ADDRESS

LINES

EFX

PERIPHERAL DEVICE

PLACES DATA IN CDP1852

AND CDP1852 SIGNALS

CDP1802 THAT DATA IS READY

VALID

THREE - STATE

DATA BUS

MRD

SR/SR

PERIPHERAL

STROBE

DATA

CDP1802 SELECTS

CDP1852 AND DATA

IS TRANSFERRED

TO MEMORY AND

THE MICROPROCESSOR

CDP1852, CDP1852C

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