M80C186 datasheet(6/59 Pages) INTEL

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M80C186

Table 1 M80C186 Pin Description

(Continued)

Symbol

PGA

QFP

Type

Name and Function

ARDY

Asynchronous Ready informs the M80C186 that the

addressed memory space or IO device will complete

a data transfer The ARDY input pin will accept an

asynchronous input and is active HIGH Only the rising

edge is internally synchronized by the M80C186 This

means that the falling edge of ARDY must be

synchronized to the M80C186 clock If connected to

VCC no WAIT states are inserted Asynchronous ready

(ARDY) or synchronous ready (SRDY) must be active

to terminate a bus cycle If unused this line should be

tied LOW to yield control to the SRDY pin

SRDY

Synchronous Ready must be synchronized externally

to the M80C186 The use of SRDY provides a relaxed

system-timing specification on the Ready input This is

accomplished by eliminating the one-half clock cycle

which is required for internally resolving the signal level

when using the ARDY input This line is active HIGH If

this line is connected to VCC no WAIT states are

inserted Asynchronous ready (ARDY) or synchronous

ready (SRDY) must be active before a bus cycle is

terminated If unused this line should be tied LOW to

yield control to the ARDY pin

LOCK

LOCK output indicates that other system bus masters

are not to gain control of the system bus while LOCK is

active LOW The LOCK signal is requested by the

LOCK prefix instruction and is activated at the

beginning of the first data cycle associated with the

instruction following the LOCK prefix It remains active

until the completion of the instruction following the

LOCK prefix No prefetches will occur while LOCK is

asserted LOCK is active LOW is driven HIGH for one

clock during RESET and then floated

S0 S1 S2

52 53 54

26 25 24

Bus cycle status S0 –S2 are encoded to provide bus-

transaction information

M80C186 Bus Cycle Status Information

Bus Cycle Initiated

Interrupt Acknowledge

Read IO

Write IO

Halt

Instruction Fetch

Read Data from Memory

Write Data to Memory

Passive (no bus cycle)

The status pins float during HOLDHLDA

S2 may be used as a logical MIO indicator and S1 as

a DTR indicator

The status lines are driven HIGH for one clock during

Reset and then floated until a bus cycle begins

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