LXT970ATC datasheet(64/74 Pages) INTEL

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LXT970A — Dual-Speed Fast Ethernet Transceiver

Datasheet

Table 45. Control Register (Address 0)

Bit

Name

Description

Type 1

Default

0.15

Reset

1 = Reset chip.

0 = Enable normal operation.

R/W

0.14

Loopback

1 = Enable loopback mode. When Loopback is enabled, during 100

Mbps operation, the LXT970A disconnects its transmitter and receiver

from the network. Data sent by the controller passes through the chip

and then gets looped back to the MII. During 10 Mbps operation the

preamble, SFD, and data loop directly back to the MII.

0 = Disable loopback mode.

R/W

0.13

Speed

Selection

1 = 100 Mbps

0 = 10 Mbps

R/W

Note 2

0.12

Auto-

Negotiation

Enable

1 = Enable auto-negotiate process (overrides speed select and duplex

mode bits).

0 = Disable auto-negotiate process.

R/W

Note 3

0.11

Power Down

1 = Enable power down.

0 = Enable normal operation.

R/W

Note 4

0.10

Isolate

1 = Electrically isolate LXT970A from MII.

0 = Normal operation.

R/W

Note 5

0.9

Restart Auto-

Negotiation

1 = Restart auto-negotiation process.

0 = Normal operation.

R/W

Note 6

0.8

Duplex Mode

1 = Enable full-duplex.

0 = Enable half-duplex.

R/W

Note 7

0.7

Collision Test

1 = Enable COL signal test. Bit 0.14 must be enabled to use this bit.

This bit is used in conjunction with bit 0.14 to test the COL output.

0 = Disable COL signal test.

R/W

Note

0.6:4

Transceiver

Test Mode

Not Supported.

0.3

Master-Slave

Enable

Not Supported.

0.2

Master-Slave

Value

Not Supported.

0.1:0

Reserved

R/W

1. R/W = Read/Write

SC = Self Clearing

2. If auto-negotiation is enabled, this bit is ignored. If auto-negotiation is disabled, the default value of bit 0.13 is determined by

pin CFG0.

3. The default value of bit 0.12 is determined by pin MF0.

4. The LXT970A internally maintains all set values of the configuration registers upon exiting power-down mode. A delay of 500

ns minimum is required from the time power down is cleared until any register can be written.

5. The default value of bit 0.10 is determined by pin TRSTE.

6. If auto-negotiation is enabled, the default value of bit 0.9 is determined by pin CFG0. If auto-negotiation is disabled, the

default value of

bit 0.9 = 0.

7. If auto-negotiation is enabled, this bit is ignored. If auto-negotiation is disabled, the default value of bit 0.8 is determined by

pin FDE.

8. This bit is ignored unless loopback is enabled (0.14 = 1).

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