LXT970ATC datasheet(16/74 Pages) INTEL

16 / 74 page

LXT970A — Dual-Speed Fast Ethernet Transceiver

Datasheet

Table 8 summarizes the relationship between input voltage levels (VMF1, VMF2, VMF3, VMF4) and

the configuration function for each of the MF input pins. Each MF pin shows two configuration

inputs; configuration function and MII address. The initial setting of the corresponding bit is also

shown.

Table 8.

MF Pin Function Settings1, 3

Input Voltage Levels2

Function

VMF1 (5V)

VMF2 (3.5V)

VMF3 (1.5V)

VMF4 (0V)

MF0

MII Address Bit 0

1100

Auto-Negotiation

Sets the initial value of bit

0.12

Disabled

(0.12 = 0)

Enabled

(0.12 = 1)

Enabled

(0.12 = 1)

Disabled

(0.12 = 0)

MF1

MII Address Bit 1

1100

Repeater / DTE Mode

Sets the initial value of bit

19.13

DTE

(19.13 = 0)

Repeater

(19.13 = 1)

Repeater

(19.13 = 1)

DTE

(19.13 = 0)

MF2

MII Address Bit 2

1100

Nibble (4B) / Symbol (5B) Mode

Sets the initial value of bit

19.4

Nibble (4B)

(19.4 = 0)

Symbol (5B)

(19.4 = 1)

Symbol (5B)

(19.4 = 1)

Nibble (4B)

(19.4 = 0)

MF3

MII Address Bit 3

1100

Scrambler Operation

Sets the initial value of bit

19.3

Enabled

(19.3 = 0)

Bypassed

(19.3 = 1)

Bypassed

(19.3 = 1)

Enabled

(19.3 = 0)

MF4

MII Address Bit 4

1100

If Auto-Negotiate Enabled via

MF0, MF4 works in combination

with CFG1 to control operating

speed and duplex advertisement

capabilities via bits 4.5 - 4.8.

See Table 9 for details.

If Auto-Negotiate Disabled via

MF0, MF4 selects either

TX or FX Mode

Sets the initial value of bit

19.2

100TX

(19.2 = 0)

100FX

(19.2 = 1)

100FX

(19.2 = 1)

100TX

(19.2 = 0)

1. In MDIO Control Mode, the MF pins control only the initial or default value for the respective register bits. In Manual Control

mode, the MF pins provide continuous control of the respective register bits.

2. Input Voltage Levels (VMF1, VMF2, VMF3, VMF4) for MF pins.

3. See Table 12 through Table 14 for operating configuration set-up.

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