80960MC datasheet(17/39 Pages) INTEL

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80960MC

PRELIMINARY

2.0

ELECTRICAL SPECIFICATIONS

2.1

Power and Grounding

The 80960MC is implemented in CHMOS IV tech-

nology and therefore has modest power require-

ments. Its high clock frequency and numerous

output buffers (address/data, control, error and arbi-

tration signals) can cause power surges as multiple

output buffers simultaneously drive new signal

levels. For clean on-chip power distribution, VCC and

VSS pins separately feed the device’s functional

units. Power and ground connections must be made

to all 80960MC power and ground pins. On the

circuit board, all Vcc pins must be strapped closely

together, preferably on a power plane; all Vss pins

should be strapped together, preferably on a ground

plane.

2.2

Power Decoupling

Recommendations

Place a liberal amount of decoupling capacitance

near the 80960MC. When driving the L-bus the

processor can cause transient power surges, partic-

ularly when connected to a large capacitive load.

Low inductance capacitors and interconnects are

recommended for best high frequency electrical

performance. Inductance is reduced by shortening

board traces between the processor and decoupling

capacitors as much as possible.

2.3

Connection Recommendations

For reliable operation, always connect unused inputs

to an appropriate signal level. In particular, when

one or more interrupt lines are not used, they should

be pulled up. No inputs should ever be left floating.

All open-drain outputs require a pull-up device.

While in most cases a simple pull-up resistor is

adequate, a network of pull-up and pull-down resis-

tors biased to a valid VIH (>3.0 V) and terminated in

the characteristic impedance of the circuit board is

recommended

limit

noise

and

power

consumption. Figure 5 and Figure 6 show recom-

mended values for the resistor network for low and

high current drive, assuming a characteristic imped-

ance of 100

Ω. Terminating output signals in this

fashion limits signal swing and reduces AC power

consumption.

NOTE:

Do not connect external logic to pins marked N.C.

Figure 4. Connection Recommendations

for Low Current Drive Network

Figure 5. Connection Recommendations

for High Current Drive Network

2.4

Characteristic Curves

Figure 7 shows typical supply current requirements

over

the

operating

temperature

range

the

processor at supply voltage (VCC) of 5 V. Figure 8

and Figure 9 show the typical power supply current

(ICC) that the 80960MC requires at various operating

frequencies when measured at three input voltage

(VCC) levels and two temperatures.

For a given output current (IOL) the curve in

Figure 10 shows the worst case output low voltage

(VOL). Figure 11 shows the typical capacitive

derating curve for the 80960MC measured from 1.5V

on the system clock (CLK) to 1.5V on the falling

edge and 1.5V on the rising edge of the L-Bus

address/data (LAD) signals.

220

Ω

330

Ω

Low Drive Network:

VOH = 3.0 V

IOL = 20.7 mA

VCC

OPEN-DRAIN OUTPUT

180

Ω

390

Ω

High Drive Network:

VOH = 3.4 V

IOL = 25.3 mA

VCC

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