80296SA datasheet(14/40 Pages) INTEL

14 / 40 page

PRELIMINARY

80296SA COMMERCIAL CHMOS 16-BIT MICROCONTROLLER

PLLEN2:1

Phase-locked Loop 1 and 2 Enable

These input pins enable the on-chip clock multiplier feature and select either the

doubled or the quadrupled clock speed:

PLLEN2

PLLEN1

Mode

1x mode; PLL disabled; f = F

XTAL

2x mode; PLL enabled; f = 2F

XTAL

Reserved †

4x mode; PLL enabled; f = 4F

XTAL

† CAUTION: This reserved combination causes the device to enter an unsupported

test mode.

PWM2:0

Pulse Width Modulator Outputs

These are PWM output pins with high-current drive capability. The duty cycle and

frequency-pulse-widths are programmable.

PWM2:0 share package pins with P4.2:0.

RD#

Read

Read-signal output to external memory. RD# is asserted during external memory

reads.

READY

Ready Input

This active-high input can be used to insert wait states in addition to those

programmed in chip configuration byte 0 (CCB0) and the bus control

x register

(BUSCON

x).

CCB0 is programmed with the minimum number of wait states (0, 5, 10, 15) for an

external fetch of CCB1, and BUSCON

x is programmed with the minimum number of

wait states (0–15) for all external accesses to the address range assigned to the

chip-select

x channel.

If the programmed number of wait states is greater than zero and READY is low

when this programmed number of wait states is reached, additional wait states are

added until READY is pulled high. If the programmed number of wait states is equal

to zero, hold the READY pin high. Programming the number of wait states equal to

zero and holding the READY pin low produces unpredictable results.

RESET#

I/O

Reset

A level-sensitive reset input to, and an open-drain system reset output from, the

microcontroller. Either a falling edge on RESET# or an internal reset turns on a pull-

down transistor connected to the RESET# pin for 16 state times.

In the powerdown, standby, and idle modes, asserting RESET# causes the

microcontroller to reset and return to normal operating mode. If the phase-locked

loop (PLL) clock circuitry is enabled, you must hold RESET# low for at least 2 ms to

allow the PLL to stabilize before the internal CPU and peripheral clocks are enabled.

After a reset, the first instruction fetch is from FF2080H.

Table 4. Signal Descriptions (Continued)

Name

Type

Description

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