ICS9178-03 datasheet(3/8 Pages) ICST

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ICS9178-03

Pin Description

*=Pin is pulled-up to VDD internally by the device.

PIN NUMBER

PIN NAME

TYPE

DESCRIPTION

XAS0

Input

LSB Programmable Group A frequency selector.

XAS1

Input

MSB Programmable Group A frequency selector.

XCLKA0

Output

TTL/CMOS group A programmable clock output.

XCLKA1

Output

TTL/CMOS group A programmable clock output.

XBS0

Input

LSB Programmable Group B frequency selector.

XBS1

Input

MSB Programmable Group B frequency selector.

XCLKB0

Output

TTL/CMOS Group B programmable clock output.

XCLKB1

Output

TTL/CMOS Group B programmable clock output.

VDDXBA

—

Power for programmable Group A and B buffers (Pins 2, 3, 5, 6).

GNDXBA

—

Ground for programmable Group A and B buffers (Pins 2, 3, 5, 6).

GNDXC

—

Ground for the programmable Group C buffers (Pins 42 and 43).

XCLKC0

Output

TTL/CMOS Group C programmable clock output.

XCLKC1

Output

TTL/CMOS Group C programmable clock output.

VDDXC

—

Power for the XC signal output buffers (Pins 42 and 43).

XCS0

Input

LSB Programmable Group C frequency selector.

XCS1

Input

MSB Programmable Group C frequency selector.

PCLK0

Output

TTL/CMOS 1X Processor clock output.

PCLK1

Output

TTL/CMOS 1X Processor clock output.

GNDP

—

Ground for PCLK output buffers (Pins 11 and 10).

VDDP

—

Power for PCLK output buffers (Pins 11 and 10).

2XPCLK0

Output

PECL 2X Processor clock output.

2XPCLK1

Output

PECL 2X Processor clock output.

EVDD

—

Power for PECL buffers (Pins 21 and 22).

EGND

—

Ground for PECL buffers (Pins 21 and 22).

EGND

—

Ground for PECL buffers (Pins 21 and 22).

38*

FS0

Input

LSB frequency select PLL (divider mode control).

37*

FS1

Input

MSB frequency select PLL (divider mode control).

FBCLK

Input

External PLL feedback path from one of the BCLK outputs.

REFCLK

Input

External reference clock input.

AVDD

—

Power for the analog PLL circuitry.

AGND

—

Ground for the analog PLL circuitry.

DCLK

Output

TTL/CMOS D clock output.

VDDD

—

Power for D output buffers (Pin 19).

GNDD

—

Ground for D output buffer (Pin 19).

BCLK0

Output

TTL/CMOS B (Bus) clock output.

BCLK1

Output

TTL/CMOS B (Bus) clock output.

GNDBAB

—

Ground for output buffers AB and B clocks (Pins 14, 15 & 18).

VDDBAB

—

Power for output buffers AB and B clocks (Pins 14, 15 & 18).

ABCLK

Output

TTL/CMOS AB Bus clock (has Asymmetric duty cycle).

TCLK

Input

External test clock input.

TEN#

Input

Test enable (tie low).

RESET#

Input

Sync register reset (active low).

VDD

—

Digital power supply for 5.0 or 3.3V.

GND

—

Digital ground supply.

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