ICS9178-03 datasheet(2/8 Pages) ICST

tên linh kiện	ICS9178-03

Giải thích chi tiết về linh kiện	245 MHz Clock Generator and Integrated Buffer for PowerPC

PDF	8 Pages

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nhà sản xuất	ICST [Integrated Circuit Systems]

Trang chủ	http://www.icst.com

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ICS9178-03

Pin Configuration

44-Pin PQFP

*VCO range is limited from 75- 245 MHz at 5V±5% and 60 - 170 MHz at 3.3V±5%. Divide ratios assume BCLK is externally

fed back to FBCLK.

_=A,B,C

Functionality

The 2XPCLK series or Thevinen trace terminations must be optimized for the specific operating frequency and board

layout. The rising edge of ABCLK is coincident with the rising edges of 2XPCLK, PCLK and other BCLKs.

X_S1

X_S0

XCLK_(0,1)

PCLK

BCLK

DCLK

Tristate

FS1

FS0

RST

TEN

*VCO

2XPCLK

PCLK

ABCLK (H/L%)

BCLK

DCLK

0010

6x REF

VCO

VCO/2

VCO/6 (66/33)

VCO/6

VCO/4

0110

8x REF

VCO

VCO/2

VCO/8 (75/25)

VCO/8

VCO/4

1010

4x REF

VCO

VCO/2

VCO/12 (50/50)

VCO/4

1110

000

0011

TCLK

TCLK/2

TCLK/6 (66/33)

TCLK/6

TCLK/4

0111

TCLK

TCLK/2

TCLK/8 (75/25)

TCLK/8

TCLK/4

1011

TCLK

TCLK/2

TCLK/12 ( 66/33)

TCLK/12

TCLK/4

1111

TCLK

TCLK/2

TCLK/4

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