PSMN3R4-30PL datasheet(7/15 Pages) NXP

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PSMN3R4-30PL

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Product data sheet

Rev. 01 — 2 November 2010

7 of 15

NXP Semiconductors

PSMN3R4-30PL

N-channel 30 V 3.4 m

Ω logic level MOSFET

[1]

Measured 3 mm from package.

td(on)

turn-on delay time

VDS =12V; RL =0.5 Ω;

VGS = 4.5 V; RG(ext) =4.7 Ω

-40

rise time

td(off)

turn-off delay time

fall time

Source-drain diode

VSD

source-drain voltage

IS =10A; VGS =0V; Tj =25°C;

see Figure 17

-0.7

1.2

trr

reverse recovery time

IS =25A; dIS/dt = -100 A/µs;

VGS =0V; VDS =12V

-36

recovered charge

Table 6.

Characteristics …continued

Tested to JEDEC standards where applicable.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Fig 5.

Output characteristics: drain current as a

function of drain-source voltage; typical values

Fig 6.

Input and reverse transfer capacitances as a

function of gate-source voltage; typical values

003aad413

120

VDS (V)

(A)

2.8

2.6

2.4

3.5

VGS (V) = 3

4.5

003aad419

1000

2000

3000

4000

5000

6000

7000

0369

VGS (V)

(pF)

Ciss

Crss

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