ICS1889 datasheet(18/35 Pages) ICST

18 / 35 page

ICS1889

Pin Definitions

MII Interface Pin Descriptions

Transmit Clock TXCLK

The Transmit Clock (TXCLK) is a continuous clock signal

generated by the ICS1889 to synchronize the Transmit

Enable, Transmit Data and Transmit Error lines. The

ICS1889 clock frequency is 25% of the nominal transmit data

rate. At 100 Mbps its frequency is 25 MHz. The TXCLK

clock duty cycle is in the range 35% to 65%.

Transmit Enable TXEN

Transmit Enable (TXEN) indicates to the ICS1889 that the

MAC is sending valid data nibbles for transmission on the

physical media. Synchronous with its assertion the ICS1889

will begin reading the data nibbles on the transmit data lines.

It is the responsibility of the MAC to order the nibbles so that

the preamble is sent first, followed by destination, source,

length, data and CFS fields since the ICS1889 has no

knowledge of the frame structure and is merely a nibble

processor. The ICS1889 terminates transmission of nibbles

following the deassertion of Transmit Enable (TXEN).

Transmit Data 3 TXD3

Transmit Data 3 (TXD3) is the most significant bit of the

transmit data nibble. TXD3 is sampled by the ICS1889

synchronously with the Transmit Data Clock when TXEN is

asserted. When TXEN is de-asserted the ICS1889 is

unaffected by the state of TXD3

Transmit Data 2 TXD2

Transmit Data 2 (TXD2) is sampled by the ICS1889

synchronously with the Transmit Data Clock when TXEN is

asserted. When TXEN is de-asserted the ICS1889 is

unaffected by the state of TXD2.

Transmit Data 1 TXD1

Transmit Data 1 (TXD1) is sampled by the ICS1889

synchronously with the Transmit Data Clock when TXEN is

asserted. When TXEN is de-asserted the ICS1889 is

unaffected by the state of TXD1.

Signal

Meaning

Signal

Meaning

TXCLK

Transmit Clock

TX+

Transmitted data positive

TXEN

Transmit Enable

TX–

Transmitted Data negative

TXD3

Transmit Data 3

IPRG

Current program

TXD2

Transmit Data 2

RX+

Receive Data positive

TXD1

Transmit Data 1

RX–

Receive Data negative

TXD0

Transmit Data 0

REF+

Frequency reference

TXER

Transmit Error

REF–

Frequency reference

RXCLK

Receive Clock

SD+

Signal Detect

RXDV

Receive Data Valid

SD–

Signal Detect

RXD3

Receive Data 3

RXD2

Receive Data 2

SYSR

System reset

RXD1

Receive Data 1

PRIO

Priority

RXD0

Receive Data 0

DPEN

Duplex Enable

RXER

Receive Error

LSTA

Link Status

CRS

Carrier Sense

P4RD

Receive data LED

COL

Collision Detect

P3TD

Transmit data LED

P2LI

Link Integrity LED

MDC

Management Data Clock

P1CL

Collision detect LED

MDIO

Management Data Input/Output

P0FD

Full duplex LED

NOD/REP

Node or Repeater Mode Selection

ICS1889 bảng dữ liệu(PDF) 18 Page - Integrated Circuit Systems

ICS1889 bảng dữ liệu(HTML) 18 Page - Integrated Circuit Systems

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35

bảng dữ liệu tải về

Link URL