HDM8515P datasheet(30/75 Pages) HYNIX

30 / 75 page

3.7 Clock Generation PLL

An integrated VCO is locked to MxN times a reference frequency provided by a external clock.

1.Determining Output Frequency

Fully programmable feedback and reference divider capability allows virtually any frequency

to be generated, not just simple multiples of reference frequency.

There are two status exist

(1) PLL Disable mode : The PLL is bypassed and the external clock is directly connected to the

Internal clock.

(2) PLL Enable mode : The internal clock is connected to the generated clock of the PLL.

1.1 PLL disable mode

PLL control setting is as follows

TDM (Bit 7 of 0x23 register) is set to one and BYPASS (Bit 4 of 0x23 register) is set to one.

1.2 Normal Frequency mode

Output frequency range is limited to 160MHz.

PLL control setting is as follows:

TDM (Bit 7 of 0x23 register) is set to zero, and BYPASS (Bit 4 of 0x23 register) is set to

zero.

At this condition, the output frequency, F(ck), is actually determined by the following

equation.

F(ck) = ----------------------------------------------

F(ck) : Frequency of output

F(ref): Frequency of reference input

Feedback divisor : M[13:0]+2 , (0x25 and 0x26 registers)

Reference divisor : N[7:0]+1 , (0x27 register)

1.3 Extended Frequency mode

Output frequency range is limited to 320MHz.

PLL control setting is as follows

TDM (Bit 7 of 0x23 register) is set to zero, and BYPASS (Bit 4 fo 0x23 register) is set to

one.

At this condition, the output frequency, F(ck), is actually determined by the following

Equation

F(ck) = --------------------------------------------------------

Pre divisor : 2

p[1:0]+1 , P is Bit 2 and 3 of 0x23 register

PLL Control Parameter setting

Besides of M (Feedback divisor), N (Reference divisor), P (Pre divisor) , You must determine vc

(VCO range control vector), lfm (Loop filter mode selector), icp (Charge pump bias current

control

F(ref) x (Feedback divisor)

(Reference divisor)

F(ref) x (Feedback divisor) x (Pre divisor)

(Reference divisor)

HDM8515P bảng dữ liệu(PDF) 30 Page - Hynix Semiconductor

HDM8515P bảng dữ liệu(HTML) 30 Page - Hynix Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75

bảng dữ liệu tải về

Link URL