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HDMP-1012 bảng dữ liệu(PDF) 19 Page - Agilent(Hewlett-Packard)

tên linh kiện HDMP-1012
Giải thích chi tiết về linh kiện  4Low Cost Gigabit Rate Transmit/Receive Chip Set
PDF  42 Pages
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nhà sản xuất  HP [Agilent(Hewlett-Packard)]
Trang chủ  http://www.home.agilent.com
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HDMP-1012 bảng dữ liệu(HTML) 19 Page - Agilent(Hewlett-Packard)

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591
Rx I/O Definition
Name
Pin
Type
Signal
ACTIVE
25
I-ECL
Chip Enable: This input is normally driven by the Rx state machine
output. The ACTIVE signal is internally retimed by STRBOUT and
presented to the user as the LINKRDY signal. This is how the Rx
state machine signals the user that the start-up sequence is complete.
BCLK
9
O-BLL
VCO Monitor Output: These pins provide access to the internal
BCLK*
8
VCO clock.
CAP0A
2
C
Loop Filter Capacitor: CAP0A should be shorted to CAP0B. CAP1A
CAP0B
1
should be shorted to CAP1B. A loop filter capacitor of 0.1
µf must be
CAP1A
3
connected across the CAP0 and CAP1 inputs to increase the loop time
CAP1B
4
constant.
CAV*
38
O-ECL
Control Frame Available Output: This active-low output indicates
that the Rx chip data outputs are receiving Control Frames. False
CAV indications may be generated during link startup.
D0
71
O-ECL
Data Outputs: 20 Bit data is received and decoded when M20SEL is
D1
70
active; otherwise 16 bit data is decoded and the D16-D19 bits
D2
69
are undefined.
D3
68
D4
67
D5
66
D6
65
D7
60
D8
59
D9
58
D10
57
D11
56
D12
55
D13
54
D14
51
D15
50
D16
49
D17
48
D18
47
D19
46
DAV*
37
O-ECL
Data Available Output: This active-low output indicates that the
Rx chip data outputs, D0..D19, have received data frames. Data
should be latched on the rising edge of STRBOUT. Note that during
link startup, false data indications may be given. The DAV* and
LINKRDY outputs can be used together to avoid confusion during
link startup.
DIN
15
I-H50
Normal Serial Data Input: This is the input used when LOOPEN
DIN*
14
is not active. When LOOPEN is high, the loop back data inputs LIN,
LIN* are used instead. An optional cable equalizer may be enabled for
the DIN, DIN* inputs by asserting EQEN.
DIV0
6
I-ECL
VCO Divider Select: These two pins program the VCO divider chain
DIV1
7
to operate at full speed, half speed, quarter speed or one-eighth speed.



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