HDMP-1012 datasheet(11/42 Pages) HP

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583

HDMP-1014 (Rx) Timing

Figure 7 is the Rx timing diagram

when the internal PLL is locked to

the incoming serial data. The

BCLK’s frequency is the same as

the input data rate. The size of

the input data frame can be either

20 bits or 24 bits, depending on

the setting of M20SEL.

Independent of the frame size,

STBROUT’s falling edge is aligned

to the data frame’s boundary,

while the rising edge is in the

center of the data frame.

The synchronous outputs, D00-

D19, LINKRDY*, DAV*, CAV*,

FF, ERROR, and FLAG, are

updated for every data frame,

with a delay of td1 after the falling

edge of STRBOUT. There is a

latency delay of two frames from

the input of the serial data frame

to the update of the synchronous

outputs.

The state machine outputs,

STAT0, and STAT1, appear with

the falling edge of STRBOUT after

a delay of td2. These outputs are

updated once every 128 frames.

HDMP-1014 (Rx) Timing Characteristics

Tc = 0

°C to +85°C

Symbol

Parameter

Units

Min.

Typ.

Max.

td1

Synchronous Output Delay

nsec

2.0

td2

State Machine Output Delay

nsec

4.0

Figure 7. HDMP-1014 (Rx) Timing Diagram.

td2

td1

D-FIELD

C-FIELD

D00 - D19

LINKRDY*

DAV*, CAV*

FF, ERROR

FLAG

STRBOUT

DIN

BCLK

STAT1

STAT0

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