HT9580 datasheet(4/63 Pages) HOLTEK

4 / 63 page

Pin Description

Pin No.

Pin Name

I/O

Description

1, 25, 56 VDD

Positive power supply

LCD_CS1

LCD driver chip select control (for slave LCD driver)

LCD_CS0

LCD driver chip select control (for master LCD driver)

LCD_CL

LCD driver clock output

LCD_A0

LCD driver data/command select control

LCD_RW

LCD Driver Read/Write signal output

LCD_E

LCD driver enable clock control

15~8

D0~D7

I/O 8-bit, tristate, bidirectional I/O data bus.

R/W

Read/Write signal output

SRAM_CE

SRAM chip Enable. This signal is generated from the HT9580 to

provide read or write timing for external SRAM devices. (See Ap-

plication Circuit)

MASK_CE

Mask ROM Chip Enable. This signal is generated from the

HT9580 to provide read timing for external Mask ROM devices.

(See Application Circuit)

Mask ROM or SRAM Output Enable. This signal is generated

from the HT9580 to provide read timing for external Mask ROM

and SRAM devices. (See Application Circuit)

PSEN

Program Store Enable. This pin is used to connect the OE and CE

pins of the external 44 Kbytes program ROM when the

²MODE_P² internal pad is connected to VSS. (See note)

21~24

RA17~RA14

Extended address bus pins

P_MODE

Internal or external program ROM selection without pull-high re-

sistor. If the pin connects to VDD, the internal program ROM will

be fetched (normal type), otherwise the external program ROM

will be fetched when the pin connects to VSS (Romless).

27, 57, 78 VSS

Negative power supply

43~28

A0~A15

Address bus pins. This is used for memory and I/O exchanges on

the data bus.

TMR1

Schmitt trigger input for timer1 counter with pull-high resisor.

45~52

PB0~PB7

I/O General Input/Output Port B. The input cell structures can be se-

lected as CMOS or CMOS with pull-high resistors.

53~54

PC0~PC1

I/O General Input/Output Port C. The input cell structures can be se-

lected as CMOS or CMOS with pull-high resistors.

Buzzer non-inverting BZ output

HT9580

April 28, 2000

Preliminary

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