HT1621 datasheet(9/20 Pages) HOLTEK

9 / 20 page

HT1621

April 21, 2000

Functional Description

Display memory - RAM

The static display memory (RAM) is organized

into 32´4 bits and stores the displayed data.

The contents of the RAM are directly mapped to

the contents of the LCD driver. Data in the

RAM can be accessed by the READ, WRITE,

and READ-MODIFY-WRITE commands. The

following is a mapping from the RAM to the

LCD pattern:

System oscillator

The HT1621 system clock is used to generate

the time base/Watchdog Timer (WDT) clock fre-

quency, LCD driving clock, and tone frequency.

The source of the clock may be from an on-chip

RC oscillator (256kHz), a crystal oscillator

(32.768kHz), or an external 256kHz clock by

the S/W setting. The configuration of the sys-

tem oscillator is as shown. After the SYS DIS

command is executed, the system clock will

stop and the LCD bias generator will turn off.

That command is, however, available only for

the on-chip RC oscillator or for the crystal oscil-

lator. Once the system clock stops, the LCD dis-

play will become blank, and the time base/WDT

lose its function as well.

The LCD OFF command is used to turn the

LCD bias generator off. After the LCD bias gen-

erator switches off by issuing the LCD OFF

command, using the SYS DIS command re-

duces power consumption, serving as a system

power down command. But if the external clock

source is chosen as the system clock, using the

SYS DIS command can neither turn the oscilla-

tor off nor carry out the power down mode. The

crystal oscillator option can be applied to con-

nect an external frequency source of 32kHz to

the OSCI pin. In this case, the system fails to

SEG 0

SEG 1

SEG 2

SEG 3

SEG 3 1

CO M 0

CO M 1

CO M 2

CO M 3

D 3

D 2

D 1

D 0

Da t a

A ddr

A ddr es s 6 bi t s

( A 5 , A 4 , ..., A 0 )

Da t a 4 b i t s

( D 3, D 2, D 1, D 0)

RAM mapping

90%

50%

10%

GN D

W R, R D

Cl o c k

t f

t r

t CL K

V DD

Figure 1

50%

VA L I D D A T A

50%

W R , R D

Cl o c k

GN D

t su

t h

V DD

GN D

Figure 2

GN D

50 %

FI R ST

Cl o c k

LA ST

Cl o c k

GN D

WR , R D

Cl o c k

t su 1

t h1

t CS

V DD

Figure 3

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