PCF8562 datasheet(19/44 Pages) PHILIPS

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PCF8562

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Product data sheet

Rev. 6 — 16 June 2011

19 of 43

NXP Semiconductors

PCF8562

Universal LCD driver for low multiplex rates

The following applies to Figure 12:

• In static drive mode the eight transmitted data bits are placed in row 0 as one byte.

• In 1:2 multiplex drive mode the eight transmitted data bits are placed in pairs into

row 0 and 1 as two successive 4-bit RAM words.

• In 1:3 multiplex drive mode the eight bits are placed in triples into row 0, 1, and 2 as

three successive 3-bit RAM words, with bit 3 of the third address left unchanged. It is

not recommended to use this bit in a display because of the difficult addressing. This

last bit may, if necessary, be controlled by an additional transfer to this address but

care should be taken to avoid overwriting adjacent data because always full bytes are

transmitted (see Section 7.10.3).

• In 1:4 multiplex drive mode, the eight transmitted data bits are placed in quadruples

into row 0, 1, 2, and 3 as two successive 4-bit RAM words.

7.10.1 Data pointer

The addressing mechanism for the display RAM is realized using the data pointer. This

allows the loading of an individual display data byte, or a series of display data bytes, into

any location of the display RAM. The sequence commences with the initialization of the

data pointer by the load-data-pointer command (see Table 12). Following this command,

an arriving data byte is stored at the display RAM address indicated by the data pointer.

The filling order is shown in Figure 12.

After each byte is stored, the content of the data pointer is automatically incremented by a

value dependent on the selected LCD drive mode:

• In static drive mode by eight

• In 1:2 multiplex drive mode by four

• In 1:3 multiplex drive mode by three

• In 1:4 multiplex drive mode by two

If an I2C-bus data access is terminated early then the state of the data pointer is unknown.

The data pointer should be re-written prior to further RAM accesses.

7.10.2 Subaddress counter

The storage of display data is determined by the content of the subaddress counter.

Storage is allowed to take place only when the content of the subaddress counter

matches with the hardware subaddress applied to A0, A1, and A2. The subaddress

counter value is defined by the device-select command (see Table 13). If the content of

the subaddress counter and the hardware subaddress do not match then data storage is

inhibited but the data pointer is incremented as if data storage had taken place. The

subaddress counter is also incremented when the data pointer overflows.

The hardware subaddress must not be changed while the device is being accessed on the

I2C-bus interface.

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