NG80386SXLP33 datasheet(49/102 Pages) INTEL

49 / 102 page

Intel386TM SX MICROPROCESSOR

Two choices of address timing are dynamically se-

lectable non-pipelined or pipelined After an idle bus

state the processor always uses non-pipelined ad-

dress timing However the NA

(Next Address) in-

put may be asserted to select pipelined address tim-

ing for the next bus cycle When pipelining is select-

ed and the Intel386 SX Microprocessor has a bus

request pending internally the address and defini-

tion of the next cycle is made available even before

the current bus cycle is acknowledged by READY

Terminating a read or write cycle like any bus cycle

requires acknowledging the cycle by asserting the

READY

input Until acknowledged the processor

inserts wait states into the bus cycle to allow adjust-

ment for the speed of any external device External

hardware which has decoded the address and bus

cycle type asserts the READY

input at the appro-

priate time

At the end of the second bus state within the bus

cycle READY

is sampled At that time if external

hardware acknowledges the bus cycle by asserting

READY

the bus cycle terminates as shown in Fig-

ure 56 If READY

is negated as in Figure 57 the

Intel386 SX Microprocessor executes another bus

state (a wait state) and READY

is sampled again

at the end of that state This continues indefinitely

until the cycle is acknowledged by READY

assert-

When the current cycle is acknowledged

the

Intel386 SX Microprocessor terminates it When a

read cycle is acknowledged the Intel386 SX Micro-

processor latches the information present at its data

pins When a write cycle is acknowledged the

Intel386 SX CPU’s write data remains valid through-

out phase one of the next bus state to provide write

data hold time

240187 – 22

Idle states are shown here for diagram variety only Write cycles are not always followed by an idle state An active bus

cycle can immediately follow the write cycle

Figure 57 Various Bus Cycles with Non-Pipelined Address (various number of wait states)

NG80386SXLP33 bảng dữ liệu(PDF) 49 Page - Intel Corporation

NG80386SXLP33 bảng dữ liệu(HTML) 49 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL