NG80386SXLP33 datasheet(28/102 Pages) INTEL

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Intel386TM SX MICROPROCESSOR

SEGMENT BASE 150

SEGMENT LIMIT 150

BASE 3124

LIMIT

DPL

TYPE

BASE

1916

2316

Type

Defines

Invalid

Available 80286 TSS

LDT

Busy 80286 TSS

80286 Call Gate

Task Gate (for 80286 or Intel386TM SX

Microprocessor Task)

80286 Interrupt Gate

80286 Trap Gate

Type

Defines

Invalid

Available Intel386TM SX Microprocessor TSS

Undefined (Intel Reserved)

Busy Intel386TM SX Microprocessor TSS

Intel386TM SX Microprocessor Call Gate

Undefined (Intel Reserved)

Intel386TM SX Microprocessor Interrupt Gate

Intel386TM SX Microprocessor Trap Gate

Figure 46 System Descriptors

Code and data segments have several descriptor

fields in common The accessed bit A is set when-

ever the processor accesses a descriptor The gran-

ularity bit G specifies if a segment length is byte-

granular or page-granular

System Descriptor Formats (Se0)

System segments describe information about oper-

ating system tables tasks and gates Figure 46

shows the general format of system segment de-

scriptors and the various types of system segments

Intel386 SX system descriptors (which are the same

as Intel386 DX CPU system descriptors) contain a

32-bit base linear address and a 20-bit segment lim-

it 80286 system descriptors have a 24-bit base ad-

dress and a 16-bit segment limit 80286 system de-

scriptors are identified by the upper 16 bits being all

zero

Differences Between Intel386TM SX

Microprocessor and 80286 Descriptors

In order to provide operating system compatibility

with the 80286 the Intel386 SX CPU supports all of

the 80286 segment descriptors The 80286 system

segment descriptors contain a 24-bit base address

and 16-bit limit while the Intel386 SX CPU system

segment descriptors have a 32-bit base address a

20-bit limit field and a granularity bit The word count

field specifies the number of 16-bit quantities to copy

for 80286 call gates and 32-bit quantities for

Intel386 SX CPU call gates

Selector Fields

A selector in Protected Mode has three fields Local

or Global Descriptor Table indicator (TI) Descriptor

Entry Index (Index) and Requestor (the selector’s)

Privilege Level (RPL) as shown in Figure 47 The TI

bit selects either the Global Descriptor Table or the

Local Descriptor Table The Index selects one of 8k

descriptors in the appropriate descriptor table The

RPL bits allow high speed testing of the selector’s

privilege attributes

Segment Descriptor Cache

In addition to the selector value every segment reg-

ister has a segment descriptor cache register asso-

ciated with it Whenever a segment register’s con-

tents are changed the 8-byte descriptor associated

with that selector is automatically loaded (cached)

on the chip Once loaded all references to that seg-

ment use the cached descriptor information instead

of reaccessing the descriptor The contents of the

descriptor cache are not visible to the programmer

Since descriptor caches only change when a seg-

ment register is changed programs which modify

the descriptor tables must reload the appropriate

segment registers after changing a descriptor’s val-

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