DP83849CVSSLASHNOPB datasheet(58/101 Pages) TI1

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7.1.10 PHY Status Register (PHYSTS)

This register provides a single location within the register set for quick access to commonly accessed information.

Table 29. PHY Status Register (PHYSTS), address 10h

Bit

Bit Name

Default

Description

RESERVED

0, RO

RESERVED: Write ignored, read as 0.

MDIX MODE

0, RO

MDIX mode as reported by the Auto-Negotiation logic:

This bit will be affected by the settings of the MDIX_EN and

FORCE_MDIX bits in the PHYCR register. When MDIX is enabled,

but not forced, this bit will update dynamically as the Auto-MDIX al-

gorithm swaps between MDI and MDIX configurations.

1 = MDI pairs swapped

(Receive on TPTD pair, Transmit on TPRD pair)

0 = MDI pairs normal

(Receive on TRD pair, Transmit on TPTD pair)

RECEIVE ERROR

LATCH

0, RO/LH

Receive Error Latch:

This bit will be cleared upon a read of the RECR register.

1 = Receive error event has occurred since last read of RXERCNT

(address 15h, Page 0).

0 = No receive error event has occurred.

POLARITY STATUS

0, RO

Polarity Status:

This bit is a duplication of bit 4 in the 10BTSCR register. This bit will

be cleared upon a read of the 10BTSCR register, but not upon a

read of the PHYSTS register.

1 = Inverted Polarity detected.

0 = Correct Polarity detected.

FALSE CARRIER

SENSE LATCH

0, RO/LH

False Carrier Sense Latch:

This bit will be cleared upon a read of the FCSR register.

1 = False Carrier event has occurred since last read of FCSCR (ad-

dress 14h).

0 = No False Carrier event has occurred.

SIGNAL DETECT

0, RO/LL

100Base-TX qualified Signal Detect from PMA:

This is the SD that goes into the link monitor. It is the AND of raw

SD and descrambler lock, when address 16h, bit 8 (page 0) is set.

When this bit is cleared, it will be equivalent to the raw SD from the

PMD.

DESCRAMBLER

LOCK

0, RO/LL

100Base-TX Descrambler Lock from PMD.

PAGE RECEIVED

0, RO

Link Code Word Page Received:

This is a duplicate of the Page Received bit in the ANER register,

but this bit will not be cleared upon a read of the PHYSTS register.

1 = A new Link Code Word Page has been received. Cleared on

read of the ANER (address 06h, bit 1).

0 = Link Code Word Page has not been received.

MII INTERRUPT

0, RO

MII Interrupt Pending:

1 = Indicates that an internal interrupt is pending. Interrupt source

can be determined by reading the MISR Register (12h). Reading

the MISR will clear the Interrupt.

0 = No interrupt pending.

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