DRGND

DRGND

AGND

ADC12DC080

SNAS405B – SEPTEMBER 2007 – REVISED NOVEMBER 2008

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Pin No.

Symbol

Equivalent Circuit

Description

The clock input pin.

18

CLK

The analog inputs are sampled on the rising edge of the clock input.

This is a two-state input controlling Power Down.

57

PD_A

20

PD_B

PD = AGND, Normal operation.

Digital data output pins that make up the 12-bit conversion result for

42-49,

DA0-DA7,

Channel A. DA0 (pin 42) is the LSB, while DA11 (pin 55) is the MSB

52-55

DA8-DA11

of the output word. Output levels are CMOS compatible.

Digital data output pins that make up the 12-bit conversion result for

23-24,

DB0-DB1,

Channel B. DB0 (pin 23) is the LSB, while DB11 (pin 36) is the MSB

27-36

DB3-DB11

of the output word. Output levels are CMOS compatible.

Data Ready Strobe. The data output transition is synchronized with

39

DRDY

the falling edge of this signal. This signal switches at the same

frequency as the CLK input.

ANALOG POWER

Positive analog supply pins. These pins should be connected to a

8, 16, 17, 58,

quiet source and be bypassed to AGND with 0.1 µF capacitors

60

located close to the power pins.

The ground return for the analog supply.

1, 4, 12, 15,

AGND

The exposed pad on back of package must be soldered to ground

Exposed Pad

plane to ensure rated performance.

DIGITAL POWER

Positive driver supply pin for the output drivers. This pin should be

26, 38,50

connected to a quiet voltage source and be bypassed to DRGND

with a 0.1 µF capacitor located close to the power pin.

The ground return for the digital output driver supply. This pins

25, 37, 51

DRGND

should be connected to the system digital ground, but not be

connected in close proximity to the ADC's AGND pins.

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

4

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