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AL8806Q bảng dữ liệu(PDF) 3 Page - Diodes Incorporated

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AL8806Q
Document number: DS36905 Rev. 1 - 2
3 of 13
www.diodes.com
April 2014
© Diodes Incorporated
AL8806Q
Recommended Operating Conditions (@TA = +25°C, unless otherwise specified.)
Symbol
Parameter
Min
Max
Unit
VIN
Operating Input Voltage relative to GND
6.0
30
V
VCTRLH
Voltage High for PWM Dimming Relative to GND
2.6
5.5
V
VCTRLDC
Voltage range for 20% to 100% DC Dimming Relative to GND
0.5
2.5
V
VCTRLL
Voltage Low for PWM Dimming Relative to GND
0
0.4
V
fSW
Maximum Switching Frequency
—
1
MHz
ISW
Continuous Switch Current
—
1.5
A
TJ
Junction Temperature Range
-40
+125
°C
Electrical Characteristics (@ VIN = 12V, TA = +25°C, unless otherwise specified.)
Symbol
Parameter
Conditions
Min
Typ.
Max
Unit
VINSU
Internal regulator start up threshold
VIN rising
—
—
5.9
V
VINSH
Internal regulator hysteresis threshold
VIN falling
100
—
300
mV
IQ
Quiescent current
Output not switching (Note 5)
—
—
350
µA
IS
Input supply Current
CTRL pin floating f = 250kHz
—
1.8
5
mA
VTH
Set current Threshold Voltage
VCTRL ≥ 2.6V or floating.
95
100
105
mV
VTH-H
Set threshold hysteresis
—
—
±20
—
mV
ISET
SET pin input current
VSET = VIN-0.1
—
16
22
µA
RCTRL
CTRL pin input resistance
Referred to internal reference
—
50
—
kΩ
VREF
Internal Reference Voltage
—
—
2.5
—
V
RDS(on)
On Resistance of SW MOSFET
ISW = 1A
—
0.18
0.35
Ω
ISW_Leakage
Switch leakage current
VIN = 30V
—
—
0.5
μA
θJA
Thermal Resistance Junction-to-
Ambient (Note 6)
(Note 7)
—
69
—
°C/W
θJC
Thermal Resistance Junction-to-Case
(Note 6)
(Note 7)
—
4.3
—
Notes:
5. AL8806Q does not have a low power standby mode but current consumption is reduced when output switch is inhibited: VSENSE = 0V. Parameter is tested
with VCTRL ≤ 2.5V
6. Refer to figure 5 for the device derating curve.
7. Measured on an FR4 51x51mm PCB with 2oz copper standing in still air with minimum recommended pad layout on top layer and thermal vias to bottom
layer maximum area ground plane. For better thermal performance, larger copper pad for heat-sink is needed.
8. Dominant conduction path via exposed pad. Refer to figure 5 for the device derating curve.



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