MPC7457 datasheet(34/71 Pages) FREESCALE

34 / 71 page

MPC7457 RISC Microprocessor Hardware Specifications, Rev. 8

Electrical and Thermal Characteristics

Freescale Semiconductor

Figure 13 provides the AC test load for TDO and the boundary-scan outputs of the MPC7457.

Figure 13. Alternate AC Test Load for the JTAG Interface

Figure 14 provides the JTAG clock input timing diagram.

Figure 14. JTAG Clock Input Timing Diagram

Figure 15 provides the TRST timing diagram.

Figure 15. TRST Timing Diagram

Valid times:

Boundary-scan data

TDO

tJLDV

tJLOV

Output hold times:

Boundary-scan data

TDO

tJLDX

tJLOX

—

TCK to output high impedance:

Boundary-scan data

TDO

tJLDZ

tJLOZ

4, 5

Notes:

1. All outputs are measured from the midpoint voltage of the falling/rising edge of TCLK to the midpoint of the signal in question.

The output timings are measured at the pins. All output timings assume a purely resistive 50-

Ω load (see Figure 13).

Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.

2. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.

3. Non-JTAG signal input timing with respect to TCK.

4. Non-JTAG signal output timing with respect to TCK.

5. Guaranteed by design and characterization.

Table 15. JTAG AC Timing Specifications (Independent of SYSCLK) 1 (continued)

At recommended operating conditions. See Table 4.

Parameter

Symbol

Min

Max

Unit

Notes

Output

Z0 = 50 Ω

OVDD/2

RL = 50 Ω

tTCLK

VM = Midpoint Voltage (OVDD/2)

tJR

tJF

tJHJL

TCLK

TRST

tTRST

VM = Midpoint Voltage (OVDD/2)

MPC7457 bảng dữ liệu(PDF) 34 Page - Freescale Semiconductor, Inc

MPC7457 bảng dữ liệu(HTML) 34 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71

bảng dữ liệu tải về

Link URL