IO13RSB0 datasheet(99/210 Pages) MICROSEMI

99 / 210 page

ProASIC3 Flash Family FPGAs

Re vi s i on 15

2 - 94

Timing Characteristics

Figure 2-34 • RAM Reset. Applicable to Both RAM4K9 and RAM512x18.

CLK

RESET

DOUT|RD

tCYC

tCKH

tCKL

tRSTBQ

Table 2-116 • RAM4K9

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V

Parameter

Description

–2

–1

Std. Units

tAS

Address setup time

0.25 0.28 0.33

tAH

Address hold time

0.00 0.00 0.00

tENS

REN, WEN setup time

0.14 0.16 0.19

tENH

REN, WEN hold time

0.10 0.11 0.13

tBKS

BLK setup time

0.23 0.27 0.31

tBKH

BLK hold time

0.02 0.02 0.02

tDS

Input data (DIN) setup time

0.18 0.21 0.25

tDH

Input data (DIN) hold time

0.00 0.00 0.00

tCKQ1

Clock High to new data valid on DOUT (output retained, WMODE = 0)

2.36 2.68 3.15

Clock High to new data valid on DOUT (flow-through, WMODE = 1)

1.79 2.03 2.39

tCKQ2

Clock High to new data valid on DOUT (pipelined)

0.89 1.02 1.20

tC2CWWL

Address collision clk-to-clk delay for reliable write after write on same

address—Applicable to Closing Edge

0.33 0.28 0.25

tC2CWWH

Address collision clk-to-clk delay for reliable write after write on same

address—Applicable to Rising Edge

0.30 0.26 0.23

tC2CRWH

Address collision clk-to-clk delay for reliable read access after write on same

address—Applicable to Opening Edge

0.45 0.38 0.34

tC2CWRH

Address collision clk-to-clk delay for reliable write access after read on same

address— Applicable to Opening Edge

0.49 0.42 0.37

tRSTBQ

RESET Low to data out Low on DOUT (flow-through)

0.92 1.05 1.23

RESET Low to Data Out Low on DOUT (pipelined)

0.92 1.05 1.23

tREMRSTB

RESET removal

0.29 0.33 0.38

tRECRSTB

RESET recovery

1.50 1.71 2.01

tMPWRSTB

RESET minimum pulse width

0.21 0.24 0.29

tCYC

Clock cycle time

3.23 3.68 4.32

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