IO13RSB0 datasheet(101/210 Pages) MICROSEMI

101 / 210 page

ProASIC3 Flash Family FPGAs

Re vi s i on 15

2 - 96

Table 2-117 • RAM512X18

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V

Parameter

Description

–2

–1

Std. Units

tAS

Address setup time

0.25 0.28 0.33

tAH

Address hold time

0.00 0.00 0.00

tENS

REN, WEN setup time

0.13 0.15 0.17

tENH

REN, WEN hold time

0.10 0.11 0.13

tDS

Input data (WD) setup time

0.18 0.21 0.25

tDH

Input data (WD) hold time

0.00 0.00 0.00

tCKQ1

Clock High to new data valid on RD (output retained)

2.16 2.46 2.89

tCKQ2

Clock High to new data valid on RD (pipelined)

0.90 1.02 1.20

tC2CRWH

Address collision clk-to-clk delay for reliable read access after write on same

address—Applicable to Opening Edge

0.50 0.43 0.38

tC2CWRH

Address collision clk-to-clk delay for reliable write access after read on same

address—Applicable to Opening Edge

0.59 0.50 0.44

tRSTBQ

RESET Low to data out Low on RD (flow-through)

0.92 1.05 1.23

RESET Low to data out Low on RD (pipelined)

0.92 1.05 1.23

tREMRSTB

RESET removal

0.29 0.33 0.38

tRECRSTB

RESET recovery

1.50 1.71 2.01

tMPWRSTB

RESET minimum pulse width

0.21 0.24 0.29

tCYC

Clock cycle time

3.23 3.68 4.32

FMAX

Maximum frequency

310

272

231

MHz

Notes:

1. For more information, refer to the application note Simultaneous Read-Write Operations in Dual-Port SRAM for Flash-

Based cSoCs and FPGAs.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

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