7

* This specification are subject to be changed without notice.

9.14.2001

EM83040B

LCD CONTROLLER

Preliminary

Preliminary

Preliminary

Preliminary

Preliminary

RAMD(3:0) are data or address of RAM. At the address mode, RAMADS is low and user should sent address

three times, from address (11:8) to address (3:0). Then it will go into data mode when RAMADS is high. In data

mode, user can sent one or more nibble data which address can be increased by internal counter.

Once the RAMEN pin is high, the RAM can not read and write.

(4) Read control

RAMEN

RAMADS

RAMD(3:0)

RAMW

RAMR

A3

A2

A1

D1

D2

D3

RAM enable

RAM disable

ADDRESS

DATA

A3=address (11:8)

A2=address(7:4)

A1=address(3:0)

Ten

Tdv

Tdh

Tdd

FIG. 4

As same as write mode, user has to sent address three times. And read data from RAM one by one which address

can be increased by internal counter. Note!! Be sure to make RAMR low pulse 2uS (Tdv +data) width and 2uS

(Tdd) high width at least.

(5) RAM mapping

RAM address is from 0 to address 2562

User fill “1” to LCD RAM, LCD driver will generate “light” waveform. Otherwise, it will generate a “dark”

waveform. The LCD RAM area is mapped to segment 1 to segment 80 from address 0 to address 19. And user

can refer to fig.5 and Table 1 to get the idea of LCD ram mapping. The other RAM can use as general RAM for

data storage if not mapping to LCD display. And the RAM of address 2560, 2561 and 2562 is control registers.

Table 1: LCD mapping RAM area

Common

Segment

Master/slave

Display area

32

48

Master

1,2,3

32

80

Slave

1,2,3,4

48

32

Master

1,2,5,6

48

80

Slave

1,2,3,4,5,6,7

64

16

Master

1,5,8

64

80

Slave

1,2,3,4,5,6,7,8,9

80

0

Master

No mapping RAM

80

80

Slave

1,2,3,4,5,6,7,8,9,10

Any

Any

Any

Area 11 is general RAM