40-bit Serial to Parallel Driver for GaAs FETs

Rev. V1

3

3

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3

MADR-011007

Bit No.

Bit Function

Bit No.

Bit Function

1

RX2-phase 1

21

TX-phase 1-A

2

RX2-phase 2

22

TX-phase 1-B

3

RX2-phase 3

23

TX-phase 2-A

4

RX2-phase 4

24

TX-phase 2-B

5

RX2-phase 5

25

TX-phase 3-A

6

RX2-phase 6

26

TX-phase 3-B

7

RX2-atten 1

27

TX-phase 4-A

8

RX2-atten 2

28

TX-phase 4-B

9

RX2-atten 3

29

TX-phase 5-A

10

RX2-atten 4

30

TX-phase 5-B

11

RX1-phase 1

31

TX-phase 6-A

12

RX1-phase 2

32

TX-phase 6-B

13

RX1-phase 3

33

TX-atten 1-A

14

RX1-phase 4

34

TX-atten 1-B

15

RX1-phase 5

35

TX-atten 2-A

16

RX1-phase 6

36

TX-atten 2-B

17

RX1-atten 1

37

TX-atten 3-A

18

RX1-atten 2

38

TX-atten 3-B

19

RX1-atten 3

39

TX-atten 4-A

20

RX1-atten 4

40

TX-atten 4-B

7. Bit No. 1 should be the first bit going into the serial interface.

Function Diagram

SNGL_DUAL

Vertical Beam Bits

L

H

TX_STATE

A

A

SNGL_DUAL

Horizontal Beam Bits

L

H

TX_STATE

L

B

A

H

B

B

TX Mux Truth Table

9. ―A‖ represents odd bits of the 20-bit TX bit stream, and ―B‖

represents even bits of the 20-bit TX bit stream.

40-bit

Shift Reg.

SERIAL IN

CLK

40-bit

Latch

40 bits

LOAD

Last 20 bits

First 20 bits

20-bit

Mux

10 TX bits

10 TX bits

20-bit

Driver

10-bit

Driver

10-bit

Driver

RX Outputs

20 RX bits

10 TX bits

10 TX bits

TX Horizontal

Outputs

TX Vertical

Outputs

Note:

Both shift registers and latches are

positive edge triggered.

SERIAL OUT

Handling Procedures

Please observe the following precautions to avoid

damage:

Static Sensitivity

Silicon Circuits are sensitive to electrostatic

discharge (ESD) and can be damaged by static

electricity. Proper ESD control techniques should

be used when handling these devices.