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HM5259165B bảng dữ liệu(PDF) 27 Page - Elpida Memory

tên linh kiện HM5259165B
Giải thích chi tiết về linh kiện  512M LVTTL interface SDRAM 133 MHz/100 MHz 8-Mword 횞 16-bit 횞 4-bank/16-Mword 횞 8-bit 횞 4-bank /32-Mword 횞 4-bit 횞 4-bank PC/133, PC/100 SDRAM
PDF  63 Pages
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nhà sản xuất  ELPIDA [Elpida Memory]
Trang chủ  http://www.elpida.com/en
Logo ELPIDA - Elpida Memory

HM5259165B bảng dữ liệu(HTML) 27 Page - Elpida Memory

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HM5259165B/HM5259805B/HM5259405B-75/A6
Data Sheet E0118H10
27
Command Intervals
Read command to Read command interval:
1. Same bank, same ROW address: When another read command is executed at the same ROW address
of the same bank as the preceding read command execution, the second read can be performed after an
interval of no less than 1 clock. Even when the first command is a burst read that is not yet finished, the data
read by the second command will be valid.
READ to READ Command Interval (same ROW address in same bank)
CLK
Command
Dout
out B3
Address
out B1 out B2
BS
ACTV
Row
Column A
READ
READ
Column B
out A0 out B0
Bank0
Active
Column =A
Read
Column =B
Read
Column =A
Dout
Column =B
Dout
CAS Latency = 3
Burst Length = 4
Bank 0
2. Same bank, different ROW address: When the ROW address changes on same bank, consecutive read
commands cannot be executed; it is necessary to separate the two read commands with a precharge command
and a bank-active command.
3. Different bank: When the bank changes, the second read can be performed after an interval of no less
than 1 clock, provided that the other bank is in the bank-active state. Even when the first command is a burst
read that is not yet finished, the data read by the second command will be valid.
READ to READ Command Interval (different bank)
CLK
Command
Dout
out B3
Address
out B1 out B2
BS
ACTV
Row 0
Row 1
ACTV
READ
Column A
out A0 out B0
Bank0
Active
Bank3
Active
Bank0
Read
Bank3
Read
READ
Column B
Bank0
Dout
Bank3
Dout
CAS Latency = 3
Burst Length = 4



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